PLL having a controller for dividing values of a VCO

ABSTRACT

A disclosed PLL can operate linearly at various frequencies by overlapping several VCOs and using a control circuit for controlling the several VCOs to select a VCO at a desired frequency. Accordingly, since the disclosed PLL can automatically pre-compensate the frequency by using control signal used in the PLL, a separate frequency correcting signal is not required. When containing a VCO, the disclosed PLL can be configured into a single chip.

BACKGROUND

[0001] 1. Technical Field

[0002] The present invention generally relates to phase locked loops(hereinafter, referred to as ‘PLL’), and more specifically, to a PLLhaving a controller for dividing values of a voltage control oscillator(hereinafter, referred to as ‘VCO’) in all the frequency band.

[0003] 2. Description of the Related Art

[0004]FIG. 1 is a block diagram illustrating a general PLL having aprogram counter.

[0005] The PLL comprises a phase comparator 1, a low pass filter LPF 2,a VCO 3 and a program counter 4. The phase comparator 1 compares areference frequency fr of an external clock signal ECLK with acomparison frequency fp of a comparison clock signal PCLK. The low passfilter LPF 2 filters an output signal from the phase comparator 1. TheVOC 3 generates a signal of frequency varying proportional to the DCsignal from the low pass filter 2. The program counter 4 divides afrequency of an output clock signal ICLK from the VCO 3 at apredetermined 1/N division ratio.

[0006] An output frequency fvco of the output clock signal ICLK from theVCO 3 is divided into 1/N by the program counter 4. The dividedfrequency negatively feeds back as the comparison frequency fp, and thenit is inputted into the phase comparator 1.

[0007] Here, the output frequency fvco from the voltage controloscillator 3 is defined by the following equation 1: $\begin{matrix}{{f\quad p} = \frac{f\quad v\quad c\quad o}{N}} & {{Equation}\quad 1}\end{matrix}$

[0008] Here, fp=fr, and [Equation 1] can be represented by the followingequation 2:

fvco=N×fr  Equation 2

[0009] Equation 2 shows that if the value of N varies, the outputfrequency fvco can be changed by the step of the reference frequency fr.

[0010] Accordingly, if the output frequency fvco is used in localoscillators of various telecommunication apparatus, one crystaloscillator can use various frequencies with the high stability. However,if the output frequency fvco becomes larger, it is difficult for theprogram counter 4 to divide the larger output frequency fvco.

[0011] Accordingly, a PLL uses a prescaler which can operate at a highspeed, as shown in FIG. 2.

[0012]FIG. 2 is a block diagram illustrating a general PLL having aprescaler.

[0013] The PLL comprises a phase comparator 11, a low pass filter 12, aVCO 13, a prescaler 14 and a program counter 15. The phase comparator 11compares a reference frequency fr of an external clock signal ECLK witha comparison frequency fp of a comparison clock signal PCLK. The lowpass filter 12 filters an output signal from the phase comparator 11.The VCO 13 generates a signal of frequency proportional to a DC signalof the low pass filter 12. The prescaler 14 divides an output signalfrom the VCO 13 into 1/M. The program counter 15 divides a clock signaldivided by the prescaler 14 into 1/N.

[0014] The output frequency fvco from the VCO 13 is divided into 1/M bythe prescaler 14. And the divided output frequency fvco is divided into1/N by the program counter 15 again. The divided frequency negativelyfeeds back as the comparison frequency fp, and it is inputted into thephase comparator 11.

[0015] Here, the comparison frequency fp is defined by the followingequation 3: $\begin{matrix}{{f\quad p} = \frac{f\quad v\quad c\quad o}{N \times M}} & {{Equation}\quad 3}\end{matrix}$

[0016] Accordingly, the output frequency fvco is defined by thefollowing equation 4. Here, fp=fr.

fvco=N×M×fr  Equation 4

[0017] In Equation 4, if the division ratio N of the program counter 15varies, the output frequency fvco is changed into a step of M×fr. As aresult, M×fr is a channel separation, which is a frequency interval ofchannel. And the reference frequency fr in a synthesizer is divisionratio 1/M of the channel separation.

[0018]FIG. 3 is a block diagram illustrating a conventional PLL having aswallow counter setting a channel separation as the reference frequencyfr.

[0019] The PLL comprises a phase comparator 21, a low pass filter 22, aVCO 23, a dual modulus prescaler 24, a program counter 25, a swallowcounter 26 and a controller 27. The phase comparator 21 compares thereference frequency fr with the comparison frequency fp. The VCO 23generates a signal of frequency proportional to a DC signal from the lowpass filter 22. The dual modulus prescaler 24 divides a frequency of anoutput clock signal ICLK from the VCO 23 into 1/M and 1/(M+1). Theprogram counter 25 divides a clock signal divided by the prescaler 24into 1/N. The swallow counter 26 divides a clock signal divided by theprescaler 24 into 1/A. The controller 27 outputs a mode control signalMC for controlling the prescaler 24 by using output signals from theswallow counter 26 and the program counter 25.

[0020] The output frequency fvco of the output clock signal ICLK fromthe VCO 23 is divided by the dual modulus prescaler 24 having divisionratios 1/M and 1/(M+1), and then the divided frequency is inputted intothe program counter 25 and the swallow counter 26.

[0021] The swallow counter 26 is used for selecting division ratios ofthe prescaler 24.

[0022] The prescaler 24 is set at a division ratio 1/(M+1) until theswallow counter 26 counts A pulses.

[0023] After the swallow counter 26 counts A pulses, the prescaler 24 isset at a division ratio 1/M. The time of A/N is a division ratio of1/[(M+1)×N], and the time of (N−A)/N is a division ratio of 1/M×N.

[0024] Here, the comparison frequency fp is defined by the followingequation 5: $\begin{matrix}\begin{matrix}{{f\quad p} = \frac{f\quad v\quad c\quad o}{\left\{ {\left( {\left( {\left( {M + 1} \right) \times N} \right) \times \frac{A}{N}} \right) + \left( {\left( {M \times N} \right) \times \frac{\left( {N - A} \right)}{N}} \right)} \right\}}} \\{= \frac{f\quad v\quad c\quad o}{\left\{ {\left( {\left( {M + 1} \right) \times A} \right) + \left( {\left( {N - A} \right) \times M} \right)} \right\}}}\end{matrix} & {{Equation}\quad 5}\end{matrix}$

[0025] Accordingly, the output frequency fvco is defined by thefollowing equation 6: $\begin{matrix}\begin{matrix}{{f\quad v\quad c\quad o} = {f\quad p\left\{ {\left( {\left( {M + 1} \right) \times A} \right) + \left( {\left( {N - A} \right) \times M} \right)} \right\}}} \\{= {f\quad {p\left( {A + {M \times N}} \right)}}} \\{= {f\quad {r\left( {A + {M \times N}} \right)}}}\end{matrix} & {{Equation}\quad 6}\end{matrix}$

[0026] In Equation 6, N is the coefficient of M, but it is not thecoefficient of A. As a result, if the value of A varies, the referencefrequency fr is changed. In this way, if the prescaler 24 is used in thePLL, the channel separation can be the reference frequency fr.Particularly, a pulse swallow is used because the prescaler 24 can beset at a high division ratio in a high-frequency synthesizer.

[0027] Generally, the output frequency fvco is defined by the followingequation 7: $\begin{matrix}{{f\quad v\quad c\quad o} = {\left\{ {\left( {M \times N} \right) + A} \right\} \times \frac{f\quad o\quad s\quad c}{R}}} & {{Equation}\quad 7}\end{matrix}$

[0028] Here, M is the division ratio of the prescaler 24, and N is theset point of the program counter 25. A is the set point of the swallowcounter 26, having a relation of A<N. In Equation 7, fosc represents thereference oscillating frequency, and R represents the set point of thereference counter.

[0029] However, the VCO of the above-described conventional PLLs cannotbe used in various frequency bandwidths due to its non-linearcharacteristic.

SUMMARY OF THE DISCLOSURE

[0030] Accordingly, the present invention has an object to operatelinearly at various frequencies by overlapping several VCOs and using acontrol circuit for selecting one VCO operating at a desired frequencyoutputted from the several VCOs, thereby satisfying characteristics ofdesign in a on-chip PLL.

[0031] There is provided a PLL comprising a phase comparator, a filter,a VCO, a prescaler, a program counter, a swallow counter, and acontroller.

[0032] The phase comparator compares a reference frequency of anexternal clock signal with a comparison frequency of a comparison clocksignal. The filter filters an output signal from the phase comparator.The VCO generates clock signal of frequency proportional to a DC signalfrom the filter. The prescaler selectively divides the output clocksignal from the VCO by using at least two or more division ratios. Theprogram counter divides an output signal from the prescaler with apredetermined division ratio to output the comparison clock signalhaving the comparison frequency. The swallow counter selects thedivision ratio of the prescaler. The controller outputs a control signalto control frequency division of the VCO by using set points of theprescaler, the swallow counter and the program counter.

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The disclosure will be described in terms of several embodimentsto illustrate its broad teachings. Reference is also made to theattached drawings.

[0034]FIG. 1 is a block diagram illustrating a general PLL having aprogram counter.

[0035]FIG. 2 is a block diagram illustrating a general PLL having aprescaler.

[0036]FIG. 3 is a block diagram illustrating a conventional PLL having aswallow counter.

[0037]FIG. 4 is a block diagram illustrating a PLL having a swallowcounter according to the present invention.

[0038]FIG. 5 is a graph illustrating an example of the frequency rangeof a RF2 VCO and the division of regions.

[0039]FIG. 6 is a circuit diagram illustrating a control bit generatorof the disclosed VCO according to the present invention.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

[0040] The present invention will be described in detail with referenceto the accompanying drawings.

[0041]FIG. 4 is a block diagram illustrating a PLL having a swallowcounter according to the present invention.

[0042] The disclosed PLL comprises a phase comparator 31, a low passfilter 32, a VCO 33, a dual modulus prescaler 34, a program counter 35,a swallow counter 36, a controller 37 and a control bit generator 38.The phase comparator 31 compares a reference frequency fr of an externalclock signal ECLK with a comparison frequency fp of a comparison clocksignal PCLK. The VCO 33 generates an internal clock signal Iclk offrequency proportional to a DC signal from the low pass filter 32. Thedual modulus prescaler 34 divides an internal clock signal ICLK intodivision ratios 1/M and 1/(M+1). The program counter 35 divides anoutput clock signal from the prescaler 34 into a division ratio 1/N. Theswallow counter 36 divides an output clock signal from the prescaler 34into a division ratio 1/A. The controller 37 controls the prescaler 34by using output signals from the program counter 35 and the swallowcounter 36. The control bit generator 38 generates a control bit CB forcontrolling the VCO 33.

[0043] An output frequency fvco from an internal clock signal ICLK ofthe VCO 33 is divided by the dual modulus prescaler 34 having divisionratios 1/M and 1/(M+1). The divided frequency is inputted into theprogram counter 35 and the swallow counter 36.

[0044] The swallow counter 36 is used for selecting one of the divisionratios of the prescaler 34. The prescaler is set at a division ratio1/(M+1) until the swallow counter 36 counts A pulses.

[0045] After the swallow counter 36 counts A pulses, the prescaler 35 isset at a division ratio 1/M.

[0046] Accordingly, the whole division value Ntotal is defined by thefollowing equation 8:

Ntotal=M×N+A  Equation 8

[0047] When the frequency division VCO 33 is used, values of N and A areused as control input values. In other words, if the control bitgenerator 38 uses the values of N and A as control input values, thefrequency division VCO 33 can be controlled. Here, it is preferable thatthe control bit generator 38 generates the control bit CB forcontrolling the frequency division VCO 33 by using the set point A ofthe swallow counter 36, the set point N of the program counter 35 andthe set point M of the prescaler 34. However, since the control bit CBbecomes larger and the circuit of the control bit generator 38 becomescomplicated, the control bit generator 38 for generating the control bitCB is explained herein by using the set point N of the program counter35 and the set point A of the swallow counter 36.

[0048] The VCO 33 receives input values N and A from the program counter35 and the swallow counter 36 to operate at a predetermined frequency,and uses the input values N and A as control values.

[0049] Accordingly, a method should be considered to satisfy the wholerange of frequency in a given variable voltage area and to reduce thevalue of actual oscillating frequency size Kvco by using an oscillatingfrequency division method.

[0050]FIG. 5 is a graph illustrating an example of the frequency rangeof a RF2 VCO and the division of regions.

[0051] Referring to FIG. 5, if the range of variable voltage is 1V inthe frequency range of GSM from 1150 MHz to 1230 MHz, the oscillatingfrequency Kvco has the value of 80 MHz/V.

[0052] However, if the frequency range is fixed at 10 MHz and a partialarea of each frequency is selected, the whole frequency range can besatisfied. The size of each oscillating frequency Kvco can be 10 MHz/V.

[0053] In the disclosed PLL, the frequency division VCO 33 is used tohave good characteristics and use broad frequency. When the outputfrequency of the frequency division VCO 33 reaches its correspondingfrequency area nearby, the disclosed PLL selects a correspondingsection.

[0054] If a voltage profit of the VCO 33 is determined, for example, as10 MHz/V, the number of the VCO 33 is determined, and then the outputcontrol bit CB from the control bit generator 38 is determined.

[0055] As a result, the output control bit CB is determined as 5 bit. Inorder to control the VCO 33 of its corresponding frequency, a look uptable is made by calculating the whole division value Ntotalcorresponding to the frequency and input values A and N corresponding tothe whole division value Ntotal. Accordingly, the control bit generator38 is designed, based on the table.

[0056] For example, in order to design the control bit generator 38which operates in 1.24968 GHz by using Equation 8, the whole divisionvalue Ntotal is first determined as 127. Then, the division value N ofthe program counter 35 is determined as 15, and the division value A ofthe swallow counter 36 as 7. As a result, the output control bit CB canbe determined.

[0057] Here, the division ratio M of the prescaler 34 is determined as8, the reference oscillating frequency fosc as 19.68 MHz, and the setpoint of the reference counter R as 2.

[0058] Accordingly, the look-up table to design the disclosed controlbit generator 38 is represented by the following Table 1. TABLE 1Control Standards Fref Ntotal A N A(bin) N(bin) bit(CB) GSM 13 88 0 110000 01011 00110 89 1 11 0001 01011 00101 90 .2 11 0010 01011 00100 91 311 0011 01011 00011 92 4 11 0100 01011 00010 93 5 11 0101 01011 00001 946 11 0110 01011 00000 AMPS/IS-95 9.84 96 0 12 0000 01100 11001 97 1 120001 01100 11000 A/C 98 2 12 0010 01100 10000 99 3 12 0011 01100 1000

[0059]FIG. 6 is a circuit diagram illustrating a control bit generator38 of the disclosed VCO 33 according to the present invention.

[0060] The control bit generator 38 comprises inverters INV1, INV2 andINV3, NOR gates NOR1, NOR2, NOR3, NOR4, NOR5, NOR6, NOR7 and NOR8, NANDgates ND1, ND2 and ND3, and a D flip-flop 40. The inverters INV1 andINV2 inverts the division value A of the swallow counter 36. Theinverter INV3 inverts the division value N of the program counter 34.The NOR gate NOR1 NORs output signals from the inverters INV1 and INV2.The NAND gate ND1 NANDs an inverted output signal from NOR gate NOR1 andthe division value A of the swallow counter 36. The NOR gate NOR2 NORsthe division value A of the swallow counter 36 and an output signal fromthe inverter INV2. The NOR gate NOR3 NORs the division value A of theswallow counter 36 and an output signal from the inverter INV1. The NORgate NOR4 NORs the division value A of the swallow counter 36 and anoutput signal from the inverter INV3. The NAND gate ND3 NANDs aninverted signal of the division value A of the swallow counter 36 andthe division value of the program counter 34. The NOR gate NOR5 NORs aninverted output signal of the NAND gate ND2 and output signals from theNOR gates NOR2 and NOR3. The NOR gate NOR6 NORs an inverted outputsignal of the inverter INV3, the division value A of the swallow counter36 and an output signal from the NOR gate NOR1. The NOR gate NOR7 NORsoutput signals from the NOR gate NOR3 and the inverter INV3. The NORgate NOR8 NORs output signals from the NOR gate NOR1 and the inverterINV3. The D flip-flop 40 includes a reset input terminal R to receivethe division value A of the swallow counter 36, a clock input terminal Cto receive the output signal from the NAND gate ND3, and a data inputterminal D to receive the output signal from the NOR gate NOR4. Thecontrol bit CB is generated by the NOR gates NOR5, NOR6, NOR7, NOR8 andthe D flip-flop 40.

[0061] Most PLLs in the current market comprise VCOs and filtersinstalled outside. These external components have a great effect on costand yield of products. Accordingly, since frequencies arepre-compensated automatically, the embodiment of the whole PLL can besimplified and compensated precisely.

[0062] As discussed earlier, in the disclosed PLL including theprescaler, frequencies can be pre-compensated automatically by using thecontrol signal used in the PLL. As a result, a separate frequencycompensation signal is not required. Additionally, when the VCO is builtin the PLL, the whole circuit of the PLL can be embodied into a singlechip.

[0063] While the invention is susceptible to various modifications andalternative forms, specific embodiments have been shown by way ofexample in the drawings and described in detail herein. However, itshould be understood that the invention is not limited to the particularforms disclosed. Rather, the invention covers all modifications,equivalents, and alternatives falling within the spirit and scope of theinvention as defined in the appended claims.

What is claimed is:
 1. A PLL comprising: a phase comparator forcomparing a reference frequency of an external clock signal with acomparison frequency of a comparison clock signal; a filter forfiltering an output signal from the phase comparator; a VCO forgenerating a clock signal of frequency proportional to a DC signal fromthe filter; a prescaler for selectively dividing the output clock signalfrom the voltage control oscillator by using at least two or moredivision ratios; a program counter for dividing an output signal fromthe prescaler with a predetermined division ratio, and outputting thecomparison clock signal having the comparison frequency; a swallowcounter for controlling the division ratio of the prescaler; and acontroller for outputting a control signal to control frequency divisionof the VCO by using set points of the prescaler, the swallow counter andthe program counter.
 2. The PLL according to claim 1, wherein theprescaler is set at large one of the two or more division ratios whilethe swallow counter operates.
 3. The PLL according to claim 2, whereinthe prescaler is set at small one of the two or more division ratioswhen the swallow counter counts a pulse by the set point.
 4. The PLLaccording to claim 2, wherein the controller is a decoder.
 5. The PLLaccording to claim 4, wherein the decoder is configured using the bitnumber of output bits, the whole counter set point, the swallow counterset point and the program counter set point.
 6. The PLL according toclaim 5, wherein the bit number of output signal is determined bydetermining voltage profit of the VCO when the set point of theprescaler is set, wherein the whole counter set point of correspondingfrequency is determined, wherein the swallow counter set point and theprogram counter set point corresponding to the whole counter set pointare determined.